Semiconductor devices are typically formed on and within semiconductor substrates, such as bulk monocrystalline silicon wafers. Electrical components formed on substrates, and particularly bulk semiconductor wafers, are located in dedicated active areas of the substrate wherein adjacent active areas are isolated from each other by insulating materials. One well-known isolation technique uses trench isolations, wherein trenches are formed into a substrate and subsequently filled with an insulating material. The insulating material is then planarized to define isolation trenches filled with insulating material that isolate adjacent active areas from each other. The etching of isolation trenches into a substrate to define active areas is also referred to as structuring of line-space patterns on the wafer.
The formation of trench isolations on structured wafers that have a non-planar top surface typically comprises several process steps. With reference to FIG. 1, a typical process for the formation of trench isolations on topology wafers is illustrated. FIG. 1 depicts a substrate 1 having a layer 3 disposed thereon. The layer 3 has an opening 10 such that a portion 2 of the substrate 1 is exposed, wherein a top surface of the substrate portion 2 is recessed below a main surface of the substrate 1. In a first step, a fill material 4, typically boro-silicate glass or spin-on glass is deposited on the layer 3 and in the opening 10. Then, a hard mask material 5 is deposited on the fill material 4 and a patterned anti-reflective coating layer 30 having a first and a second trench 27a, 27b extending along a lateral direction X is formed on the hard mask material 5, wherein the first and second trenches 27a, 27b each are located above outer portions of the fill material 4 inside the opening 10 and above portions of the layer 3 adjacent to the fill material 4 in the opening 10. The first and the second trench 27a, 27b of the patterned anti-reflective coating layer 30 each have a lateral dimension S0 along the direction Y as depicted in FIG. 1, wherein S0 is referred to as space width. A remaining portion 30a of the patterned anti-reflective coating layer 30 located between the first and second trenches 27a, 27b has a lateral dimension L0 along the direction Y as depicted in FIG. 1, wherein L0 is referred to as line width.
Thereafter, a first etching step I is performed in which the hard mask material 5 is etched selectively to the patterned anti-reflective coating layer 30 to form a patterned hard mask, and thereby exposing portions of the fill material 4. Subsequently, a second etching step II is performed in which the layer 3 and the fill material 4 are etched selectively with respect to the patterned hard mask. In a third etching step III, the substrate 1 is etched through openings of the hard mask and through openings of the fill material to form a first and a second isolation trench 11a, 11b. The resulting first and second isolation trenches 11a, 11b are depicted in FIG. 1 by dashed lines.
Each of the first I, second II and third III etching steps are typically performed in a dry etching tool by a reactive ion etching (RIE) or dry etching process. The RIE process comprises flowing a gas including suitable etchants to the substrate and operating a lower RF source and an upper RF source of the dry etching tool at specific power levels.
However, the lateral dimensions S0 of the trenches 27a, 27b of the patterned anti-reflective coating layer 30 may not be transferred directly to the underlying material when reactive ion etching is performed. The resulting lateral dimensions of the trenches in the underlying material may be wider or smaller than the lateral dimensions of the trenches 27a, 27b of the patterned anti-reflective coating layer 30. This phenomenon is well-known as Reactive Ion Etching (RIE) lag.
In the case that the substrate portion 2 comprises an oxide material, the selectivity between the fill material that comprises an oxide and the substrate is very low during the third etching step III. Therefore, the lateral dimensions of the resulting isolation trench in the substrate are much wider than the lateral dimensions of the opening of the hard mask.
With reference to FIGS. 2A and 2B, the lateral dimensions space width (S) and line width (L) are depicted dependent on the position in the direction Z as shown in FIG. 1. The Z-position “1” relates to the interface between the hard mask material 5 and the fill material 4, the Z-position “2” relates to the interface between the layer 3 and the substrate 1 and the Z-position “3” relates to a bottom of the isolation trenches 11a, 11b disposed in the substrate 1.
As depicted in FIG. 2B, the space width strongly increases during the third etching step III from S2 to S3. Accordingly, the first and second etching steps I, II have to be adapted to provide a very small space width S2 after the second etching step II has been performed to form isolation trenches having the desired lateral dimension. However, for even higher integration, the space width S2 approaches zero. Accordingly, the current integration scheme is limited.
It is desirable to provide an improved method of forming a semiconductor device.